1. Field of the Invention
The present invention relates to a self-synchronous logic circuit having a test function and to a method of testing a self-synchronous logic circuit. More specifically, the present invention relates to a self-synchronous logic circuit having a function of testing a logic circuit having a self-synchronous pipeline and to a method of testing a self-synchronous logic circuit.
2. Description of the Background Art
Generally, a logic circuit in an LSI (Large Scale Integration) forms a pipeline in which a plurality of stages are connected in series, with state storing elements such as flip-flops serving as boundaries. Data processing in the pipeline proceeds such that the data to be processed is input to a head stage of the serial connection (hereinafter simply referred to as the head stage), processing is done in each stage, and eventually, a result of processing is output from the last stage. In a synchronous circuitry, all the stages of the pipeline operate in synchronization with a common clock. Logic circuits, however, come to have ever increasing scale, higher speed of operation, and smaller design rule, and therefore, it becomes more and more difficult to attain clock distribution with adjusted delays that is necessary in physical design of synchronous circuits over an entire chip or an entire module. Accordingly, LSI logic circuits such as a data driven processor having a self-synchronous pipeline have been proposed, in which clock distribution is performed only within the stages of the pipeline, and clocks are transferred by handshake between the stages of the pipeline so as to eliminate the necessity of a common clock to attain synchronization. Each stage of the pipeline of the data driven processor includes a self synchronous signal control circuit handling clock transfer, and a circuit for data processing. In the entire pipeline, the former is in charge of clock transfer, and the latter provides a data path. (In the following description, the stage of interest will be sometimes referred to as the present stage, the stage preceding the stage of interest will be simply referred to as the preceding stage, and the stage succeeding the stage of interest will be simply referred to as the succeeding stage. Further, the n-th stage from the head stage will be simply referred to as the n-th stage.)
FIG. 8 shows a characteristic portion of a conventional logic circuit having a self-synchronous pipeline. Referring to FIG. 8, pipeline stage registers (hereinafter simply referred to as registers) 804, 805 and 806 each constitute a stage of the pipeline successively transferring a data path input from a preceding stage to a succeeding stage. Between an output of register 804 and an input of register 805, a combination circuit 107 is connected, and between an output of register 805 and an input of register 806, a combination circuit 108 is connected. Combination circuits 107 and 108 process data output from registers 804 and 805 of the preceding stages, respectively, and are formed simply by a combination of basic gate circuits, without any circuit such as a flip-flop for holding an internal state.
Corresponding to registers 804, 805 and 806, self-synchronous signal control circuits 801, 802 and 803 are provided, respectively. Self-synchronous signal control circuits 801, 802 and 803 handshake with each other while outputting, from a terminal CP, clock pulses to the corresponding registers. Upon reception of the clock pulses from the corresponding self-synchronous signal control circuits, registers 804, 805 and 806 take data from the preceding stage, hold the same and output to the succeeding stage.
FIG. 9 is a specific block diagram of the self-synchronous signal control circuit shown in FIG. 8. Referring to FIG. 9, a request signal CI representing, by two states of the signal, transfer request and transfer complete is input from the preceding stage to a CI input terminal 201. An RO output terminal 202 returns to the preceding stage an acknowledge signal RO that represents, by two states of the signal, transfer permission permitting output of the transfer request of the request signal CI from the preceding stage, and transfer reception indicating reception of the transfer request. In accordance with the request signal CI of the preceding stage indicating transfer complete and the acknowledge signal RI from the succeeding stage indicating transfer permission, a CP output terminal 205 issues a clock pulse for storing data in the register. A CO output terminal 203 applies, through a delay element 210 to the succeeding stage, a request signal representing, by two states of the signal, transfer request and transfer complete. An RI input terminal 204 receives, from the succeeding stage, an acknowledge signal RI representing, by two states of the signal, transfer permission permitting output of the transfer request from the CO output terminal 203 to the succeeding stage, and transfer reception indicating reception of the transfer request by the succeeding stage.
Further, the self-synchronous signal control circuit includes a flip-flop 901, a 4-input NAND gate 209 and a flip-flop 208. Flip-flop 901 holds a transfer request receiving state, flip-flop 208 holds a transfer request issuing state for the succeeding stage, and NAND gate 209 attains synchronization among flip-flops 901, 208, the CI input and the RI input. The request signal CI is input to an S input terminal of flip-flop 901, and the request signal CI is also applied to one input terminal of NAND gate 209. A Q output signal of flip-flop 901 is applied to one input terminal of NAND gate 209, and a Q-inverted output (/Q) of flip-flop 901 is output to an RO output terminal 202. The RI signal that has been input to RI input terminal 204 is applied to one input of NAND gate 209 and a reset input terminal of flip-flop 208. An output signal of NAND gate 209 is applied to a reset input terminal of flip-flop 901 and to a set input terminal of flip-flop 208. The Q output of flip-flop 208 is output to a CP output terminal 205, and the Q-inverted output (/Q) is applied to a CO output terminal 203 and to NAND gate 209.
An MRB input terminal 206 supplies a reset signal MRB for setting flip-flops 901 and 208 to the initial state.
FIGS. 10A to 10L are timing charts illustrating the operation related to FIGS. 8 and 9. The timing charts represent changes of signals related to self-synchronous signal control circuit 801 at CI input terminal 801CI, CO output terminal 801CO, RI input terminal 801RI, RO output terminal 801RO, and CP output terminal 801CP. Similarly, changes of signals related to self-synchronous signal control circuit 802 at CI input terminal 802CI, CO output terminal 802CO, RI input terminal 802RI, RO output terminal 802RO and CP output terminal 802CP are represented, and changes of signals related to self-synchronous signal control circuit 803 at CI input terminal 803CI, CO output terminal 803CO, RI input terminal 803RI, RO output terminal 803RO and CP output terminal 803 CP are represented. FIGS. 10A to 10L represent an operation when transfer request/complete is input once, with the stages of the pipeline being empty. Timings T1 to T4 are indicated in FIGS. 10B and 10C to facilitate understanding of the operation. The operation will be described with reference to FIGS. 8, 9 and 10A to 10L.
First, flip-flops 901 holding transfer request receiving state and flip-flops 208 holding the transfer request issuing state of the self-synchronous signal control circuits of all the stages are reset by a pulse input of the reset signal MRB shown in FIG. 10A. At this time, RO output terminals are at the transfer permission state of H, and the CO outputs are at the transfer complete state of H in all self-synchronous signal control circuits.
To the CI input terminal 801CI of self-synchronous signal control circuit 801 as the first stage of the pipeline shown in FIG. 8, a transfer request by the request signal CI shown in FIG. 10B is input (see timing T1: change from H to L, first way of the handshake between the input and the first stage). In response, flip-flop 901 holding the transfer request receiving state of self-synchronous signal control circuit 801 is set, and from the RO output terminal 801RO of self-synchronous signal control circuit 801 to the preceding stage of the pipeline, transfer reception by the acknowledge signal RO shown in FIG. 10C is output (see timing T2: change from H to L, second way of the handshake between the input and the first stage). About that time, data to be processed is input to a data path input of register 804.
Thereafter, to the CI input terminal 801CI of self-synchronous signal control circuit 801, transfer complete is input by the request signal CI shown in FIG. 10B (see timing T3: change from L to H, third way of the handshake between the input and the first stage), and in response, NAND gate 209 is activated. Thus, flip-flop 208 holding the transfer request issuing state of self-synchronous signal control circuit 801 is set, the CP output terminal 801CP of self-synchronous signal control circuit 801 changes from L to H as shown in FIG. 10D (that is, a clock pulse is output), and data is latched in register 804. At the same time, from the CO output terminal 801CO of self-synchronous signal control circuit 801 to the second stage of the pipeline, transfer request by the request signal CO shown in FIG. 10E is output through delay element 210 (change from H to L, first way of the handshake between the first stage and the second stage), and NAND gate 209 of self-synchronous signal control circuit 801 is inactivated. Thus, flip-flop 901 holding the transfer request receiving state is reset. Then, from the RO output terminal 801RO of self-synchronous signal control circuit 801 to the preceding stage, transfer permission by the acknowledge signal RO shown in FIG. 10C is output (see timing T4: change from L to H, fourth way of the handshake between the input and the first stage).
To the CI input terminal 802CI of self-synchronous signal control circuit 802 as the second stage of the pipeline, a transfer request is input by the request signal CI shown in FIG. 10E (change from H to L, first way of the handshake between the first stage and the second stage), and in response, flip-flop 901 holding the transfer request receiving state of self-synchronous signal control circuit 802 is set. Then, from the RO output terminal 802RO of self-synchronous signal control circuit 802 to the first stage of the pipeline, transfer reception by the acknowledge signal RO shown in FIG. 10F is output (change from H to L, second way of the handshake between the first stage to the second stage).
About that time, processed data that has been processed by combination circuit 107 is input to a data input of register 805. To the RI input terminal 801RI of self-synchronous signal control circuit 801 as the first stage of the pipeline, transfer reception by the acknowledge signal RI shown in FIG. 10F is input (change from H to L, second way of the handshake between the first stage and the second stage), and in response, flip-flop 208 holding the transfer request issuing state of self-synchronous signal control circuit 801 is reset. The CP output terminal 801CP of self-synchronous signal control circuit 801 attains from H to L, and at the same time, from the CO output terminal 801CO of self-synchronous signal control circuit 801 to the second stage of the pipeline, transfer complete by the request signal CO shown in FIG. 10E is output through delay element 210 (change from L to H, third way of the handshake between the first stage and the second stage).
When the transfer complete is input (change from L to H, third way of the handshake between the first stage and the second stage) to the CI input terminal 802CI of self-synchronous signal control circuit 802 as the second stage of the pipeline, NAND gate 209 of self-synchronous signal control circuit 802 is activated. In response, flip-flop 208 holding the transfer request issuing state of self-synchronous signal control circuit 802 is set, the CP output terminal 802CP of self-synchronous signal control circuit 802 attains from L to H as shown in FIG. 10G, and data is latched in register 805. At the same time, from the CO output terminal 802CO of self-synchronous signal control circuit 802 to the third stage of the pipeline, transfer request by the request signal CO shown in FIG. 10H is output through delay element 210 (change from H to L, first way of the handshake between the second stage and the third stage), and NAND gate 209 of self-synchronous signal control circuit 802 is inactivated. Thus, flip-flop 901 holding the transfer request receiving state of self-synchronous signal control circuit 802 is reset, and from the RO output terminal 802RO of self-synchronous signal control circuit 802 to the first stage of the pipeline, transfer permission by the acknowledge signal RO shown in FIG. 10F is output (change from L to H, fourth way of the handshake between the first stage and the second stage).
The operation proceeds in the similar manner between the second stage and the third stage. The CP output terminal 802CP of self-synchronous signal control circuit 802 changes from H to L as shown in FIG. 10G, the CP output terminal 803CP of self-synchronous signal control circuit 803 changes from L to H, and then further changes from H to L as shown in FIG. 10J. At this time, the CO output terminal 802CO and the RI input terminal 802RI of self-synchronous signal control circuit 802 change as shown in FIGS. 10H and 10I. Thereafter, the CO output terminal 803CO and the RI input terminal 803RI of self-synchronous signal control circuit 803 change as shown in FIGS. 10K and 10L.
In this manner, in response to the transfer request represented by transfer request signals CI and CO, clock pulses and data are transferred through the pipeline (or a plurality of stages), by four-way handshakes between the self-synchronous signal control circuits.
FIGS. 11A to 11L are timing charts of another exemplary operation of the self-synchronous signal control circuits shown in FIG. 8, representing an operation in which transfer permission/reception is input once with all the stages of the pipeline being full with data. By the reset signal MRB shown in FIG. 11A, the entire circuitry is reset, and thereafter, by the acknowledge signal RI, the transfer reception state of L shown in FIG. 11L is input to the RI input terminal 803RI of self-synchronous signal control circuit 803 as the third stage, that is, the last stage of the pipeline. In this state, by the request signal CI, transfer request (change from H to L)/complete (change from L to H) shown at timings T1 and T3 of FIG. 11B is input three times to the CI input terminal 801CI of self-synchronous signal control circuit 801 as the first stage of the pipeline. Accordingly, as can be seen at timings T2 and T4 of FIG. 11C, the signal at RO output terminal 801RO of self-synchronous signal control circuit 801 of the first stage stops at T2 of the third operation. During this period, the transfer request/complete shown in FIG. 11E is input twice to the CI input terminal 802CI of self-synchronous signal control circuit 802 of the second stage, and the transfer request/complete shown in FIG. 1H is input once to the CI input terminal 803CI of self-synchronous signal control circuit 803 of the third stage. As a result, the stages of the pipeline are filled with data. Thus, the circuitry is in a state waiting for a transfer permission from the acknowledge signal RI shown in FIG. 11L (the state after the third way of the handshake among all the stages).
Thereafter, when transfer permission (change from L to H)/reception (change from H to L) is input to the RI input terminal 803RI of self-synchronous signal control circuit 803 as the third stage, that is, the last stage of the pipeline, by the acknowledge signal RI, the transfer permission/reception signal is propagated in a direction opposite to the direction of the data flow through the pipeline, in the order of terminal 803RO of FIG. 11Ixe2x86x92 terminal 802RI of FIG. 11Ixe2x86x92 X terminal 802RO of FIG. 11Fxe2x86x92 terminal 801RI of FIG. 11Fxe2x86x92terminal 801RO of FIG. 11C, through connection from acknowledge signal RO to RI. Correspondingly, clock pulses are also generated in a direction opposite to the direction of the data flow through the pipeline, in the order of terminal 803CP of FIG. 11Jxe2x86x92 terminal 802CP of FIG. 11G terminal 801CP of FIG. 11D.
The operation at this time including the register side is as follows. Upon reception of transfer permission of the succeeding stage of the pipeline, the third stage, that is, the last stage, of the pipeline latches the output from combination circuit 108 in register 806, and thereafter, applies transfer permission to the second stage of the pipeline. In response, the second stage of the pipeline latches the output from combination circuit 107 in register 805, and thereafter applies transfer permission to the first stage of the pipeline. In response, the first stage of the pipeline latches the data from the data path input. As can be understood, the operation is under the severest hold timing condition for the registers.
By connecting the necessary number of stages in such a pipeline configuration as shown in FIG. 8, it becomes possible to realize the series of data processing without necessitating clock distribution over the entire chip or module.
It is a general practice to perform a test on an LSI before shipment to confirm whether circuits are manufactured without any defect, by inputting test signals to all logic circuits. In order to perform a test to detect any defect in combination circuits between stages of a pipeline of an LSI, it is necessary to input data of necessary and sufficient number of patterns to the input of the combination circuit for each stage of the pipeline, and to compare the outputs with the expected values.
As the LSI comes to have larger scale and hence larger number of stages in the pipeline, it becomes difficult to apply desired inputs to combination circuits of intermediate stages and to obtain outputs therefrom, and long test vector length and long period of vector development are required.
For this reason, scan test method is generally used for circuits that operate in accordance with a common clock, in which each register is adapted to have a function enabling switching between a normal input and test input, and for an input of a test, outputs of other registers are connected in a string. Here, the shift register path that is formed by connecting in string the registers one by one is generally referred to as a scan chain.
FIG. 12 shows an example of a synchronous circuitry operating in accordance with a common clock corresponding to the scan test method. The synchronous circuitry shown in FIG. 12 includes scan compliant registers (hereinafter simply referred to as registers) 104, 105 and 106, and combination circuits 107 and 108 not having any internal state, performing operations and the like between the stages of the pipeline. Referring to FIG. 12, a common clock CLK and a scan test enable signal SE are supplied to each of the registers 104 to 106. The scan test enable signal SE is a signal for switching whether the scan chain is to be made valid or not.
Registers 104, 105 and 106 including the scan chain each have the same configuration shown in FIG. 13. Referring to FIG. 13, each register includes selectors 13011, 13012, 13013 to 1301n, registers 13021, 13022, 13023 to 1302n, a terminal 1308 receiving as an input the common clock CLK, terminals 13031, 13032, 13033 to 1303n receiving as inputs normal data D0, D1, D2 to Dn, terminals 13041, 13042, 13043 to 1304n outputting latched normal data Q0, Q1, Q2 to Qn, a terminal 1305 to which input data SI to the scan chain is supplied, a terminal 1306 providing an output data SO from the scan chain, and a terminal 1307 for receiving as an input the scan test enable signal SE.
When the scan chain in invalid, each register performs a normal operation in which normal data D0, D1, D2 to Dn input every time the common clock CLK is input is latched. When the scan chain is valid, values of the registers are shifted-in from the data input side of the scan chain and shifted-out to the data output side of the scan chain simultaneously, in accordance with the order of connection of the scan chain, every time the common clock CLK is input.
Overall scan test procedure will be described. First, the scan test enable signal SE is input to make the scan chain valid, and input data SI that has been set to a desired test value is set in the internal registers through the scan chain. Thereafter, the scan test enable signal SE is input to make the scan chain invalid, one pulse of common clock CLK is input to latch the output of a combination circuit between each of the stages of the pipeline, the scan test enable signal SE is again input to make the scan chain valid, and the value latched in the register is taken out through the scan chain and compared with the expected value. At the same time, a next test input value is set in the internal register through the scan chain. The circuitry is tested by repeating this procedure.
By using this scan test method, it becomes possible to set a desired input value and to take out an output value through the scan chain, from an intermediate stage of a pipeline consisting of multiple stages, and therefore, even a large scale circuit can be tested.
The above described scan test, however, requires the common clock CLK at the time of testing. Therefore, this cannot be applied to the self-synchronous pipeline shown in FIG. 8. Though the self-synchronous pipeline facilitates physical design of LSIs that come to have larger scale, higher degree of miniaturization and higher speed of operation, it still has a problem that testing becomes more difficult as the circuit scale becomes larger.
In view of the foregoing, the applicant proposed a circuit configuration shown in FIG. 14 as a solution to this problem, in Japanese Patent Laying-Open No. 2002-5997 entitled xe2x80x9cSelf-Synchronous Logic Circuit Having Test Circuit.xe2x80x9d
The circuitry shown in FIG. 14 includes registers 104, 105 and 106 having a configuration similar to that shown in FIG. 13 including a scan chain, scan test compliant self-synchronous signal control circuits 1401, 1402 and 1403, combination circuits 107 and 108 performing an operation and the like between stages of the pipeline and not having any internal state, and a selector 1406.
Selector 1406 switches and outputs, based on an input scan clock switching signal 1404, either an applied acknowledge signal RI of a normal handshake or a scan test clock 1405.
The scan test compliant self-synchronous signal control circuits 1401 to 1403 of FIG. 14 each have the same configuration shown in FIG. 15. Referring to FIG. 15, the circuit includes a CI input terminal 201 receiving as inputs transfer request and transfer complete represented by two states of the request signal CI from the preceding stage of the pipeline, an RO output terminal 202, a CO output terminal 203 transmitting the transfer request and the transfer complete to the succeeding stage of the pipeline, an RI input terminal 204, a CP terminal 205, an input terminal 206 for the reset signal MRB, and a terminal 1503 receiving as an input the scan clock switching signal 1404. In a normal operation, RO output terminal 202 returns transfer permission permitting an output of transfer request and transfer reception indicating receipt of the transfer request from CI input terminal 201, represented by two states of the signal, to the preceding stage of the pipeline, and in a scan test operation, the terminal directly outputs the scan clock signal input from RI input terminal 204. In a normal operation, RI input terminal 204 receives transfer permission permitting output of the transfer request and transfer reception indicating receipt of the transfer request from CO output terminal 203, represented by two states of the signal, from the succeeding stage of the pipeline, and in a scan test operation, receives as an input the scan clock. In a normal operation, in accordance with receiving transfer complete from the preceding stage of the pipeline and transfer permission from the succeeding stage of the pipeline, CP terminal 205 supplies a clock pulse to the register of the present stage, and at the time of a test, the terminal directly outputs the scan clock signal input from RI input terminal 204.
The circuit of FIG. 15 further includes a delay element 210 delaying the transfer request/complete signal, a flip-flop 901 holding a transfer request receiving state from the preceding stage of the pipeline, a flip-flop 208 holding a transfer request issuing state to the succeeding stage of the pipeline, an NAND gate 209 establishing synchronization between the CI input and the RI input as well as flip-flop 901 and flip-flop 208, a selector 1501 for switching which of the transfer permission/reception signal and the scan clock input from the succeeding stage of the pipeline through RI input terminal 204 is to be provided to RO output terminal 202, and a selector 1502 for switching which of the normal clock generated as a result of a handshake and the scan clock input from the succeeding stage of the pipeline through RI input terminal 204 is to be provided to CP output terminal 205. Reset signal MRB functions to set flip-flops 901 and 208 to the initial state.
By this configuration, signal levels of CP output terminals 205 of scan test compliant self-synchronous signal control circuits 1401, 1402 and 1403 can be determined by the scan clock provided from RI input terminals 204 through RO output terminals 202 of the scan test compliant self-synchronous signal control circuits at the time of a scan test, and therefore, a common clock can be supplied to the scan test compliant registers 104, 105 and 106, which means that the scan test method is applicable to this circuitry.
By the circuitry shown in FIGS. 14 and 15, a configuration is provided that enables application of the scan test to the self-synchronous pipeline. In this configuration, however, timings must be carefully adjusted to avoid a problem of hold timing at the time of a scan test, by performing clock distribution with delays aligned to some extent for the scan clock used at the time of a scan test, or by adding a delay cell or delay cells in a path of propagating the scan clock from the acknowledge signal RI input to the acknowledge signal RO output, to intentionally shifting the phases of the scan clock between the stages of the pipeline.
When the former approach is taken, the advantage of the self-synchronous pipeline that facilitates physical design by performing clock distribution only within the stages of the pipeline is lost. When the latter approach is taken, a delay cell of a relatively large size is required separately.
In the configuration above, the clock system used at the time of a scan test is fundamentally switched from the clock system used in a normal operation. Therefore, clock phase relation between the stages of the pipeline at the time of a scan test is different from that in a normal operation. This means that a timing test in a normal operation must be performed separately. Particularly, in a hold timing test, stages of the pipeline must be operated filled with process data, as shown in the timing charts of FIGS. 11A to 11L. Therefore, the test is very difficult.
An object of the present invention is to provide a self-synchronous logic circuit having a function of enabling an easy test by a simple configuration, and to provide a method of testing a self-synchronous logic circuit.
In order to attain the above described objects, the present invention provides, according to an aspect, a self-synchronous logic circuit having a test function including registers holding data and connected in multiple stages for a pipeline, and a self-synchronous signal control circuit provided corresponding to each of the registers.
When transfer permission is applied to a preceding stage of the pipeline in the first way, the self-synchronous signal control circuit receives as an input transfer request from the preceding stage of the pipeline together with data output from the register of the preceding stage of the pipeline, upon reception of the transfer request, applies transfer reception to the preceding stage of the pipeline in the second way, when the transfer reception is received by the preceding stage of the pipeline, receives as an input transfer complete from the preceding stage of the pipeline in the third way, and when the transfer complete is received and transfer permission is applied from the succeeding stage of the pipeline in the fourth way, applies transfer permission to the preceding stage of the pipeline, makes the register take and hold data from the preceding stage of the pipeline, output the data to the succeeding stage of the pipeline and applies transfer request to the succeeding stage of the pipeline.
The register has a function of successively transferring data in a normal operation and at the time of a test. At the time of a test, all the self-synchronous signal control circuits are set to the state of the third way of handshaking, and thereafter, transfer permission and transfer reception are applied to the self-synchronous signal control circuit of the last stage of the pipeline.
Therefore, at the time of a test, all the self-synchronous signal control circuits are set to the state of the third way, and thereafter, when transfer permission and transfer reception are applied to the self-synchronous signal control circuit of the last stage of the pipeline, all the self-synchronous signal control circuits make a transition to the fourth way successively in a direction from the last stage to the head stage of the pipeline, with the data from a preceding stage of the pipeline taken and held by the register and successively output to the register of a succeeding stage of the pipeline.
Therefore, even at the time of a test, data transfer procedure in accordance with four-way handshake can be utilized, and hence it is unnecessary to adjust with care timings of data transfer separately. The data hold timing test can be performed using the same timings as in a normal four-way handshake.
In the self-synchronous logic circuit having the test function described above, preferably, setting of all the self-synchronous signal control circuits to the state of the third way at the time of a test, and application of transfer permission and transfer reception to the self-synchronous signal control circuit of the last stage of the pipeline, are repeated.
Therefore, at the time of a test, all the self-synchronous signal control circuits make transition to the fourth way successively and repeatedly in the direction from the last stage to the head stage of the pipeline without applying any special timing signal, and all the data held in the stages of the pipeline can be transferred and provided.
Preferably, the self-synchronous logic circuit having the above described test function further includes a last stage signal processing unit for applying, at the time of a test, transfer request output by the self-synchronous signal control circuit of the last stage of the pipeline to the succeeding stage of the pipeline as transfer permission from the succeeding stage of the pipeline, to the self-synchronous signal control circuit itself.
Therefore, at the time of a test, every time the self-synchronous signal control circuit of the last stage of the pipeline makes a transition to the fourth way and applies transfer request to the succeeding stage of the pipeline, the transfer request is automatically applied as transfer permission by the last stage signal processing circuit to itself. Therefore, all the data held in the stages of the pipeline can surely be transferred and provided without applying any special timing signal.
Preferably, in the self-synchronous logic circuit having the test circuit described above, setting of all the self-synchronous signal control circuits to the state of the third way at the time of a test, application of transfer permission and transfer reception to the self-synchronous signal control circuit of the last stage of the pipeline, and application of transfer request and transfer complete to the self-synchronous signal control circuit at the head stage of the pipeline are repeated.
Therefore, at the time of a test, after all the self-synchronous signal control circuits make transition to the fourth way successively and repeatedly in a direction from the last stage to the head stage of the pipeline, transfer request and transfer complete are applied repeatedly to the self-synchronous signal control circuit of the head stage of the pipeline. Therefore, all the self-synchronous signal control circuits make transition to the first to the third ways successively and repeatedly in a direction from the last stage to the head stage of the pipeline. Therefore, the operation of supplying data from the head stage of the pipeline, transferring data and providing data at the last stage of the pipeline can be repeated without applying any special timing signal.
Preferably, the self-synchronous logic circuit having the test function described above further includes a head stage signal processing unit for applying, at the time of a test, transfer request output from the self-synchronous signal control circuit of the head stage of the pipeline to the succeeding stage as a transfer request to the self-synchronous signal control circuit itself.
Therefore, at the time of a test, every time the self-synchronous signal control circuit of the head stage of the pipeline makes a transition to the fourth way and applies transfer request to the succeeding stage of the pipeline, the transfer request is automatically applied to itself as transfer request by the head stage signal processing unit. Accordingly, all the self-synchronous signal control circuits make transition to the first to the third ways successively and repeatedly in a direction from the last stage to the head stage, without applying transfer request and transfer complete to the self-synchronous signal control circuit of the head stage of the pipeline. Therefore, the operation of supplying data from the head stage of the pipeline, transferring data, and providing data at the last stage of the pipeline can be repeated without applying any special timing signal.
According to an aspect, the present invention provides a method of testing a self-synchronous logic circuit for testing a self-synchronous logic circuit including registers holding data and connected in multiple stages for a pipeline, and a self-synchronous signal control circuit provided corresponding to each of the registers, the self-synchronous signal control circuit processing data while performing four-way handshake in which when transfer permission to a preceding stage is applied in a first way, a transfer request from the preceding stage is received as an input together with data output from the register of the preceding stage of the pipeline, upon input of the transfer request, transfer reception is applied to the preceding stage of the pipeline in a second way, when the transfer reception is received as an input by the preceding stage of the pipeline, transfer complete is received as an input from the preceding stage of the pipeline in a third way, and when the transfer complete is received as an input and transfer permission is applied from the succeeding stage of the pipeline in a fourth way, transfer permission is applied to the preceding stage of the pipeline and data from the preceding stage of the pipeline is taken and held by the register and data is output to the succeeding stage of the pipeline to apply transfer request to the succeeding stage of the pipeline. The register has a function of successively transferring data in a normal operation and at the time of a test. The method of testing includes the state setting step of setting all self-synchronous signal control circuits to the state of the third way of handshake at the time of a test, and after the setting by the state setting step, the step of applying transfer permission and transfer reception to the self-synchronous signal control circuit of the last stage of the pipeline.
Therefore, at the time of a test, after all self-synchronous signal control circuits are set to the state of the third way, when transfer permission and transfer reception are applied to the self-synchronous signal control circuit of the last stage of the pipeline, all self-synchronous signal control circuits make transition to the fourth way successively in a direction from the last stage to the head stage of the pipeline, and the data held in each of the registers are successively transferred to the register of the succeeding stage.
Therefore, even at the time of a test, the data transfer procedure of four-way handshake can be utilized, and therefore, it is unnecessary to adjust with care timings of data transfer separately, and a data hold timing test can be performed in accordance with the normal four-way handshake.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.